Universal logic circuitry having modules with minimum input-output connections and minimum logic gates

ABSTRACT

Universal logic circuitry for a large number of variables using identical universal logic circuits of a small number of variables having a minimal number of logic gates and input-output circuits as modules in a multilevel arrangement.

United States Patent 3,579,119 [72] Inventors Silt-Sang Yau; [50] FieldofSearch 307/203. Calvin K. Tang, Evanslon. III. 207; 328/92-6, l58;235/1 50.53 [2|] Appl. No. 724,701 22 1 Filed Apr. 29. I968 ReferencesCited [45] Patented May 18, I971 UNITED STATES PATENTS 1731 Assignee3,090,943 5/l963 Lewis 32s/92x Evanston, Ill.

Primary Examiner-Donald D. Forrer Assistant Examinerlohn Zazworsky [54]UNIVERSAL LOGIC CIRCUITRY HAVING Altomeylohnson, Dienner, Emrich,Verbeck & Wagner MODULES WITH MINIMUM INPUT-OUTPUT CONNECTIONS ANDMINIMUM LOGIC GATES 2] Chums Drawing Figs ABSTRACT: Universal logiccircuitry for a large number of [52] U.S.Cl 328/92, variables usingidentical universal logic circuits of a small 307/203, 307/207, 328/93number of variables having a minimal number of logic gates [51] Int. ClH03k 19/00, and input-output circuits as modules in a multilevelarrangeflOOXl Al HOIXI ment.

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UNIVERSAL LOGIC CIRCUITRY HAVING MODULES WITH MINIMUM INPUT-OUTPUTCONNECTIONS AND MINIMUM LOGIC GATES FIELD OF THE INVENTION Universallogic circuits which are used to realize logic functions for three. fourand more variables; the circuits may have different fan-in limitationsand may be used to provide larger universal logic circuits (ULC) ofamore complex, economical and reliable structure, or as a building blockfor realizing arbitrary functions. In addition. the invention isdirected to an arrangement which uses an error correction code toimprove the reliability ofa ULC.

DESCRIPTION OF PRIOR ART In order to achieve a significant economicadvantage in utilizing integrated circuits in computer circuitry, it isdesirable and necessary to provide a circuit which can provide any logicfunction of a fixed number of variables by simply varying its inputterminal connections. Such a circuit is called a universal logic circuit(ULC). When the number of variables of alarge number of variables. Themodules of a small number of variables are called universal logicmodules (ULMs).

The problem of designing a ULC was first treated by D. C. Forslund andR. Waxman, The Universal Logic Block (ULB) and Its Application To LogicDesign. IEEE Publication l6C40 pp. 236-350. and later by .l. T. Ellisonet al. Universal Function Modules," UNIVAC Tech. Report, Contract No.AFl9-28-60l 2, DDCAD-655395 Apr. 1967, and by B. EI- spas et al.,Properties of Cellular Arrays For Logic and Storage," Stanford ResearchInstitute Scientific Report 3, Contract No. AF-l9-628-5828. DDC AD-65883June 1967. Such arrangements employed the concept of equivalence classesto reduce the number of all possible logic functions of a given numberof variables to the number of the equivalence classes. An equivalenceclass is a set of logic functions that may be obtained from a particularnetwork by only manipulating the application of variables to the inputterminals of the network. One of the most common constraints on thesemanipulations is that only true variables are available with thepermutation of the variables at the input terminals permitted. With thisrestriction, L. Hellerman A Catalogue of Three- Variables OR-INVERT andAND-INVERT Logical Circuit" IEEE Transaction on Electronic ComputersVol. 12, pp. 198- 223, 1963 partitioned the 2 =256 three-variable logicfunctions into 80 equivalence classes. In order to reduce the number ofequivalence classes, Forslund and Waxman assumed that both true andcomplement variables are available at the input, and true and complementlogic functions are both available at the output (two output terminals).In addition, biasing (to a logical l or and duplication of inputvariables to the input terminals are also permitted. The equivalenceclasses defined this way reduces its number from 80 to II) forthree-variable logic functions.

SUMMARY OF THE INVENTION It is an object of the present invention toprovide universal logic circuits which may be used to realize logicfunctions for three, four and more variables, or as a building block forrealizing more complex, larger arbitrary functions.

It is another object of the present invention to provide a universallogic circuit of a minimal number of gates and a minimal number ofinput-output pins for use in providing universal logic circuits of alarge number of variables.

It is a further object of the invention to provide a universal logiccircuit for any arbitrary three-variable logic function by a basiccircuit which has only seven gates, and only seven input-output pins. Inone embodiment, in realizing the logic function of three variables x,,x,x five gates (without inverters) provide the desired output functions.Briefly, the circuit is arranged to provide the logic function f(x,,x,x,,) of three variables x,,x ,x;, by connecting the variables over theinput terminals to reflect the expansion,

frog/"(1.01 +x x- -f(1. 1. x where the functionsf(0, O, x;,),f(0, l,x),f( 1,0, x,,) andf( l, I, x are functions of x only, and each of thesefunctions assumes one of the four values: 1: I 0, or I. In the novelthree variable circuit of the invention, five logic gates are connectedin two levels (not including the inverters) to realize any arbitrarythree-variable logic function f(x., x x by connecting two inputs of eachof four gates to two of the groups 1.,1 and I I, inputs, and the otherinput of each of the four gates to one of the groups of four inputs x I0, and l to reflect the expanded function. The fifth gate is connectedto the outputs of the four gates.

It is yet another object of the invention to provide a universal logiccircuit for any arbitrary four-variable logic function by a basiccircuit which has only l4 gates and only I 1 inputoutput tenninals witha fan-in limitation of five or 12 gates and I2 input-output tenninalswith a fan-in limitation of eight.

It is a further object of the invention to provide a universal logiccircuit for any arbitrary four-variable logic function by a basiccircuit which has l6 gates (including inverters) and 12 input-outputterminals.

In the foregoing objects in which circuits for three and four variablesare described the circuits may be extended to provide a larger number ofvariables n.

It is a further object of the invention to provide a novel multilevelULC in which the function of a large number of n variables is realizedby using ULM-k modules in successive levels in a tree structure.

BRIEF DESCRIPT ION OF DRAWINGS In the accompanying drawings: FIG. 1 is aULC of three variables consisting of AND, OR and NOR gates;

FIG. 2 is a ULC of three variables consisting of NOR gates only;

FIG. 3 is a ULC of three variables consisting of OR, NAND and INVERTERgates;

FIG. 4 is a ULC of four variables with two levels and a fan-in FIG. 5 isa ULC of four variables with three levels and a fanin 5;

FIG. 5A is a ULC of four variables with four levels and a fan-in 4;

FIG. 6 is a ULC of five variables;

FIG. 7 is a showing of a type I ULC-n;

FIG. 8 is a modular realization of a ULC of seven variables usingULM-Ss;

FIG. 8A is a modular realization of a ULC of n variables using ULM-3s;

FIG. 9 shows a circuit in which a check bit is applied to a ULC todetect a single fault;

FIG. I0 is a modular realization of a ULC of n variables usingsingle-error-correcting code; and

FIG. II is a ULC of three variables implemented with diode resistorlogic elements.

GENERAL DESCRIPTION With reference to FIG. 1, there is shown thereat anembodiment of the novel circuit for providing any arbitrarythreevariable logic function flx gr gc As there shown, a first inputterminal C, and a second input terminal C and input terminals A -A areconnected to the inputs for four logic gates l0, l2, l4 and I6respectively. The outputs II, l3, l5, 17 of gates l0, l2, l4, 16 areconnected over an OR gate 18 to provide the function output f( x x xover the output terminal F.

Input terminals C C extend x x, inputs via conductors 21, 22 and arealso connected over inverters 19, 20 to provide 2,,

Y2 inputs over conductors 23. 24. Gate 10 has its three inputs connectedto conductors 24. 23 (E. E and A to provide the function i, .Y flO, O, xat its output 11. Gate [2 has its three inputs connected to conductors24. 21 (K, 1: and A to pro vide the function I, .r f((). l,x;.l at itsoutput I3. Gate 14 has its inputs connected to conductors 22, 23 (.n. E)and A to provide the function x, 3 F( l. U. x at its output 15. and gateI6 has its input connected to conductors 21. 22 (x,. x and A to providethe function x, x f( l, L1 at its output l7.

By way of example, it will be assumed that the circuit of FIG. I is tobe used to provide the function f(x, 1: x for .r -hr x such functionhaving been selected in the first instance for the purpose of providinga simple example of the utility of the present circuit.

It will be apparent that for each of the residue functions the followinginputs are required:

Xvi- 2753 Output [loam becomes... (J+('(l)(x;)==0 u f(0,l,xzi becomes"0+(l)(x )=tta XII [(l,(],xu) becomes. 1+(D)(X:) 1 t(l,1,x3, becomes1+(I)(X3l=l+tts 1 To provide such outputs A is connected to logic 0, A,is

To provide such outputs A is connected to 3, etc.

It can be shown that the basic ULC shown can be connected to providef(x, x x for any three-variable functions by using the proper inputterminal connections.

It will be apparent from the foregoing description that one novelembodiment of the three-variable ULC comprises seven gates including twoinverters in the input circuit, four logic gates. and a gate in theoutput circuit. If the circuit shown in FIG. I is to be a minimum gatecircuit, inverters I9, 20 may be omitted and two extra input pins '13,.i; may be provided.

It is further apparent that the two level AND and OR circuits can bereplaced by NAND gates of the same configuration. Thus inverter circuits1), 20, AND gates l0, l2, l4 and I6, and OR gate in FIG. 1 may bereplaced by NAND gates to provide a like mode of operation while yetstandardizing on the gates to be used.

In the embodiment of the ULC shown in FIG. I as well as in the NAND gateconfiguration described, the basic circuit in one example may comprise16 diodes and seven input-output pins (i.e., three diodes for gates l0,l2, l4, 16, four diodes for gate I8 and a transistor for gates I9 and20). For example, the ULC shown in FIG. II comprises 16 diodes d,d andseven input-output terminals C',, C' A,,A and F. Diodes d.-

d d.,-d,,, (t -d and ri -11, comprise AND gates l0, 12,

I4, and I6, respectively and diodes ai -d connected to the outputs ofgates 10', 12', I4 and 16' comprise an OR gate I8. Gates 10, 12', 14',I6 and 18 correspond to gates I0, 12, 14, 16, and 18 of the ULC ofFIG. 1. Similarly, input terminals C, C and AR -A, correspond toterminals C,, C,.

that any logical gate of known design may be used to replace theseexemplary gates.

A UIJC of three-variables consisting of only NOR gates is shown in FIG.2. It is noted that the configuration of NOR gates 30, 32, 34. 36. 38,39 and 40 of the ULC of FIG. 2 is similar to the configuration shown inFIG. I including gates 10. I2, i4, 16. [8, I9 and 20 with the exceptionof the permutation of the input values for the front terminals A,, A,,.That is, input terminal A in FIG. 2 is connected to an input for thelower logic gate 36, input terminal A, is connected to the next logicgate (34) from the bottom, input terminal A is connected to an input onlogic gate 32 and input terminal A is connected to an input on logicgate 30. This will be seen to be an inverse manner of connection ascompared with the input connections shown in FIG. 1.

In a further embodiment shown in FIG. 3, NAND, OR and inverter gates areused to provide the desired functions. It will be apparent that in FIG.3 complement inputs are provided. While such circuit requires differentgates, one advantage of the ULC of FIG. 3 over those shown in FIG. 2 isthe fact that 16 diodes and three transistors may be used, while thecircuit shown in FIG. 2 requires l6 diodes and seven transistors. Thecircuit shown in FIG. 3 provides a much stronger output signal ascompared to that provided by the circuit of FIG. 1. A similar circuitcan obviously be provided with AND, NOR and INVERTER gates. In each ofthe circuits described above. a minimum of seven l/O pins is required.

To evaluate the ULC circuit described hereinabove, a comparison with theresults given by Forslund and Waxman is made as follows: With referenceto the circuit shown in FIG. 2, as a minimum-pin ULC, and assuming gates39 and 40 are included in the ULC. it will be seen that the circuit hasseven pins, seven gates, and three levels (the inverters constitute thethird level). The minimum-pin ULC of three variables given by Forslundand Waxman also has seven pins, but it requires 10 gates and has fivelevels. The ULC shown in FIG. 2 also has the advantage that only onecomplement input is required, whereas the minimum-pin ULC given byForslund and Waxman requires two complement inputs. If the circuit shownin FIG. 2 is to be considered as a minimum-gate ULC, gates 39 and 40 canbe excluded from the ULC at the expense of adding two more input pins(3,, i whereby the circuit will comprise a minimum-gate ULC of fivegates, nine pins and two levels. The minimum-gate ULC of the prior artidentified above has six gates, nine pins and four levels, and canrealize only the logic functions in nine out of the 10 equivalenceclasses.

It will be seen that the absolute minimum number of gates required forany ULC of three variables is five (not including the two inverters),since the realization of the exclusive-orfunction of three variables(with the complemented input variables alone requires a minimum of fiveNAND gates.

Summarily, the logic circuit shown in FIGS. 1, 2, 3, with six inputterminals C C A A A A and one output terminal F will produce thefunction f(x,, x x at the output terminal F if the six input terminalsare connected to the proper values shown in FIGS. 1, 2 and 3. Theresidue functionsflO, 0, x f(0, l, x;,),f( l. 0, x and f( l, 1, x arefunctions of x only, and hence each of these functions assumes one ofthe four values x i 0 or I. For the same reason, the logic circuitsshown in FIGS. 2 and 3 can also produce f(x ,x ,x and the proper inputterminal connections are shown in the circuits. Therefore, each of thethree logic circuits shown in FIGS. 1, 2 and 3 is a ULC-3. In fact, alogic circuit with six input terminals C C A A A and A, and one outputten'ninal F is a ULC-3 if the logic circuit gives the output (i [theoutput function f(x,,x ,x at the output terminal F where d;, is

:t i 2 L0+ |C2G +C a +c c a and C ,cz,aq a fl2 and 0 are the inputvariables connected to the input terminals C,,C ,A ,A,,A, and A;,,respectively. Such circuit will produce f(x,x,x if terminals C ,C ,A ,AA and A are connected to x x f(0,0,x ),j(0,l ,x I ,0,x ),f(l,l ,xrespectively. The ULC3 with this property is called Type I ULC-3, (FIG.I for example).

A circuit with six input terminals C C A A A and A connected to theinput variables c ,c ,a ,a,,a-,, and a respectively and producing anoutput e at the output terminal F of the circuit is a ULC-3 if fu .1 xif terminals C,. C .A ,,,A,. A. and A, are connected to x,, x f(0,0,x,,),f(0, l ,x;,)f( 1,0. x:,l.ft I. l.x 1) respectively. Such a circuit isa Type II ULC 3. Both logic functions d and a; are functions of sixvariables and e =d;;. The two types of ULC-3 are specified by the twologic functions (i and e of six variables. An example of Type II ULC-Jis shown in FIG. 3.

UNIVERSAL LOGIC CIRCUITS OF FOUR AND MORE VARIABLES The problem ofdesigning a ULC of four or more variables was also treated in the priorart (Forslund and Waxman), using the same idea of equivalence classes asin the case of three-variable ULC. Due to the large amount ofcomputations required, it is prohibitive to obtain such a ULC by thatmethod. However, the novel circuitry used in the present invention forobtaining the ULC of three variables can readily by extended to four ormore variables. Since a logic function f(x,, x x 1,) of four variablescan be written in the form Such a circuit will produce the ULC of fourvariables shown in FIG. 4 is obtained. It is noted that there is a NANDgate with a fan-in of 8 in the illustrated embodiment.

Briefly, the ULC for four or more variables comprises eight logic NANDgates such as 70, 72, etc., three input NAND gates 87-89 and an outputNAND gate 86. Each logic gate such as 70, 72, has four inputs includingone from each of the four groups x,,, i x I A], 2,; and the inputappearing at the terminals It -A the input connection of each gate tothe first three groups (1 I etc.) being determined by the functionrepresented by the corresponding one of the inputs A A,. Thus gate 70which provides the output f, i, i -,f(0,0,0, x.) has a first inputconnected to conductor 96 (3,), a second input connected to conductor 94(i and a third input connected to conductor 92 (f and a fourth conductorconnected to terminal A The connections for the remaining gates 72, 74etc., will be apparent therefrom. The output signals from logic gate 70,etc., are fed over NAND gate 86 to output terminal 98.

It will be apparent that the novel ULC for four variables shown in FIG.4 comprises only 12 NAND gates in a basic configuration of minimumcomplexity.

Summarily, a Type I ULC-4 is specified by function d of l I variables asfollows:

A circuit with ll input terminals C ,C ,C ,A ,A,,...,A connected toinput variables c,,c,,c,-,,a ,a,,...,a,, respectively producing theoutput function d, is a Type I ULC-4. In order to produce a logicfunction f(x,,r ,.t,,r of four variables, input terminals C,,C ,C,,A,A,,...,A are connected to x,,x,,xfl0.0.0.x,,).fl0.0,l..t.,)f(l).]..0,x,).f(0.1. I.x J,f(I,0.0,xf(l,0,l,x,),fll,l,0,x ),f( I,l,l,x.,), respectively. An example ofType IULC-4 is shown in FIG. 4.

Similarly, a Type II ULC-4 is specified by the following function e, ofl 1 variables:

=Z The manner of implementing such function with gates will be apparentfrom the disclosure of the ULC-4's above.

If the addition of further gates can be justified, the inputs to thelogic gates may be reduced as shown in FIG. 5. In such arrangement, oneof the input terminals of the group C C C is connected to the outputside of the logicgates over two NAND gates to a common NAND gate and theoutput terminal Fv Thus, in FIG. 5 the input terminals C C and A,,--Ainput connections are unchanged from that shown in FIG. 4; however, theinputs to terminals A,,A, are complements of those shown in FIG. 4, andthe logic gates, such as I00, I02, etc., do not have an IQ, 2?. input.Instead, the outputs of the logic gates I00, I02, 104, I06 are connectedto NAND gate 119 and an I, input is fed thereto by NAND gate 117 andconductor 118. In a similar manner the output of gates I08, I10, H2, H4is fed to NAND gate 121 along with the x, input on conductor I16. Theoutput of NAND gates I19, 121 is fed over conductors 120, 122 to NANDgate I23 and output conductor I24 to provide the function f(x,,x ,.x-,,x.,) output. Although such arrangement requires more gates than thecircuit shown in FIG. 4, it will be seen that the fan-in limitations tothe gates I00, 102, etc., is reduced, while yet practicing the basicconcept of the invention. As in the case of three-variable ULC's, thecorresponding embodiments of FIGS. 4 and 5 using NOR gates will use thesame configurations of the original NAND realizations with their inputterminal connections permutated. The rule of permutation on the residuefunctions of one variable for the NOR realization is to replace l by 0and O by l in the residue functions for a NAND realization. Forinstance,f(0, I, 0, x,) in FIG. 4 would be replaced by f( l,(), l, x,)for the corresponding connection in the embodiment utilizing NOR gates.

In the circuit shown in FIG. 5A the fan-in limitation is reduced tofour. The connection of the gates in such FIG. will be apparent from thepreceding description of FIGS. 4 and 5v ULCs of five or more variablescan be derived in a similar way, one embodiment of such structure beingshown in FIG. 6. The ULC of five variables shown in FIG. 6 has a fan-inlimitation of four. It is, of course, possible to further reduce thenumber of gates if a large fan-in is permitted. As there shown, 16 logicgates, such as 130, 132, etc., each have three input terminals, one ofwhich is connected to one input of the group function f(0, 0, 0, 0,x,,)f( l, I, l, I, x another input terminal of which is connected to oneof the groups 1: L, and a third input terminal of which is connected toone of the groups 1 I The l6 gates are divided into groups of four, eachof which groups is connected over an associated NAND gate, such as 165,to a further level. Thus, the output of the first group of four gatesI30, I32, 134, 136 are fed to gate I65, the outputs of the second group138, 140, 142, 144, is connected over NAND gate I67, to the furtherlevel, etc. The further level includes a second set of logic gates I85,187, 189, 188, each gate of which has one input terminal connected toone of the groups of inputs x,, a second input terminal connected to oneof the groups of inputs x,, I, and a third input terminal connected tothe output of one of the logic gates I65, I67, I69, 171. The outputofgates I85, 187, 189, 191 is connected over conductors 186, I88, 190,192 and NAND gate 193 to provide the logic function f(x,, x x 1: x overoutput conductor 195.

UNIVERSAL LOGIC CIRCUIT OF n VARIABLES (ULCn) The method used in theabove description to obtain ULC-3, UCL-4, ULC-5 can be readily extendedto obtain ULC-n. The Type I ULC-n is specified by the p=2""+n-alvariables function:

form the binary representation respectively and producing the functionat, at the output terminal F is a type I ULC-n. To obtain any n-variablefunction fII'.l'g-.. ..r..l. the input terminal (T, is connected tox.'(l si s n- II and A lflsjil" I) toftj,.y;....,j,..,.x,.l. where j j-...j,. is the binary representation of j. An example of Type 1 ULC-n isshown in FIG. 7.

It will be recalled that the circuit of FIGS. 1 and 2 is specified byfUl'tCIIOfl 3 i 2fl0 1 1 1 1 2% r 2 3- With reference to the generalfunction d above (1 l it will be apparent that for a three variablelogic circuit the function becomes As noted above, the superscript i,i...i,,,, forms the binary representation of i. Thus, in the example:

i o s E fl i z i HEP-O I,

j: I: j:

Similarly, Type II ULC-n is specified by the p-variable function P J Anycircuit with p input terminals C ,C ,....C,,-r. Ar|,A .....A connectedto the input variables 6 .c c vl, anu afi-k respectively and producingthe output function e, at the output terminal F is a Type II ULC-n. Toobtain any n-variable function f(x,,x,,...,x,,), the input terminal C,is setstite mei mem t9.1' "-F to fthJ -J x"). wherejtit..j,,..l is thebinary representation ofj. I

It can also be shown that a ULC of n variables obtained by each of theforegoing circuits shown in FIGS. l7 has p input pins, where With afan-in limitation of four, this approach will yield a ULC of nvariables, n 2, which has q gates and 1 levels, where It is noted thatfor any n only one complementary input variable is required, and allothers can be true input variables in a ULC obtained by this method.

n when n is odd n+1 when n is even A UNIVERSAL LOGIC CIRCUIT USINGUNIVERSAL LOGIC MODULES In the foregoing disclosure. there is set forththe manner in which a ULC of any large number of variables may beprovided. However, it follows that the complexity of the ULC increasesrapidly as the number of variables increases. From either an economicalpoint of view or maintenance point of view, it becomes prohibitive tobuild ULCs of various large numbers of variables in individualintegrated circuit packages. According to the present invention, a ULCof a large number of variables is provided by using identical ULCs of asmall number of variables as modules. Obviously, there art twoadvantages of such technique. First, a large quantity of identical ULM'smay be used to build ULCs of various numbers of variables. Secondly,when there are faults in a ULC, it is only necessary to replace thefaulty ULM's instead of the whole ULC.

ULC MODULES OF N VARIABLES (N ODD) In deriving the modular realizationof a ULC of n variables using ULC's of three variables as the ULMs(denoted by ULM-S's), the first embodiment considered is the case when nis odd. Since any logic function (f(x .x ...,x,,) ofn variables. n23.can be expanded to the form such module can be provided by a ULM-3,provided that the side terminals C and C and the front terminals A A Aand A shown in FIGS. 1 or 2 are connected to the input variables x, andx and the residue functions f(0,0,x ,...,x, fl0,1 ,x ,...,x,,), f(1,0,x,...,x,.) and f( l,l,x ,...,x,,) respectively. This ULM-3 forms thefirst level of the modular realization of the ULC. Since this processcan be repeated to each of the residue functions, the second level ofthe modular realization consists of four ULM-S's whose side terminalsare connected to the input variables x and x and whose front terminalsare connected to appropriate residue functions of n-4 variables. Suchprocess is continued until the residue functions become functions of thevariable x Because n is odd, and because each expansion reduces thenumber of variables of the residue functions by exactly 2, it requires atotal of (21-1 )[2 expansions. This implies thatf(.x,,...,x,,) can berealized by using ULM-3s in a tree structure consisting of (ri-1)/2levels, as shown in FIG. 8a. It is seen that there are 4" ULM-3s inthejth level of the tree structure. Each of the front terminals of theULM-3's in the last level is connected to one of the four values 0, l,Jr, and I defined by the corresponding residue function of variable x,which can be found as follows:

a. Trace the path from the output terminal F to the front terminal inthe last level in question in the tree structure, and use two bits towrite the binary representation of the subscript h for the frontterminal A, of the ULM-3 in each level.

b. The concatenation of the (n-l 2 2-typles in the order of the pathforms the argument of the residue function for the front terminal. Forinstance, if the path from the output terminal to a front terminal inthe last level in a modular ULC of five levels passes through the frontterminals A,, A A A A of the ULM-3s in the lst, 2nd... 5th levelsrespectively, the residue function for this terminal isf(0, l ,l,0,0,0,l,l ,0,l ,x For convenience, we shall call the front terminal ofa ULM-3 in the last level P, if it is connected to the residue functionwith the binary argument whose decimal representation is i. It isobvious that there are 2'" front terminals of the ULM-3s in the lastlevel for a modular ULC of n variables. The application of such teachingto a modular embodiment of a ULC of 7 variables using ULM-Ss is shown inFIG. 8.

As there shown, f(x,,...,x can be realized by using ULM-3s in a treestructure consisting of (7-1 )/2=3 levels. It is seen that there are 4 416 ULM-3s in the third level of the tree structure. Each of the frontterminals of the ULM-3s in the last level is connected to one of thefour values 0, l, x, and i defined by the corresponding residue functionof variable x,.

(N EVEN) When n is even and when only ULM-3's can be used in the modularrealization, only slight modification in the first level is required.Instead of expanding the logic function according to the form used forthe first level when n is odd, the logic function is expanded asfollows: flx x x,,)=i,fl0.x ,,x )-l-x fl1 ,x ,...,x,,). It is easilyseen that such expansion can be realized by a ULM-3, provided that theside terminals C and C are both connected to the input variable x thefront terminals A and A connected to the residue functions fl0,x,...,x,.) and f(l,x .""-x,) respectively, and the connections for A, andA are don't-care. Then, each of the residue functions is a function ofan odd number of variables and hence can be realized by the previousmethod. The residue functions for the front terminals of the ULM-3s inthe last level can be found in the same way as before except that onlythe first bit in the binary argument of the residue function correspondsto the subscript of the front terminal of the ULM3 in the first level.The first bit is or 1 depending upon whether the front terminal of theULM-3 in the first level in the path is A or A respectively.

Summarily, a ULC of a large number of variables can be realized by usingULC s of a smaller number of universal logic modules (ULMs). Expandingthe logic function offofn variables:

where the subscripts l lg l k form the binary representation of l', and1f=i ,,i =x (l$js/.l). Thusfcan be realized by a Type I ULC of kvariables (ULM-k), provided that the input terminals C, are connected tox,( leisk-I and input terminals A; are connected to fit} i ,,,,,i ,t a-i z where i|i2, l k 1 is the binary representation of l'(0 i 2-'- l).This Type I ULM-J: forms the first level of the modular realization ofthe ULCl1. This process is repeated to each of the residue functionsfli, i ,,,,il.--l,xi xi-t xll)- and the second level of the modularrealization consists of 2' Type I U LM--ks. Each of these second levelULMJcs will have the input terminals C, connected to input variablesedia's/r1) and input terminals A connected to the appropriate residuefunctions of rl2(kl variables. As the process is continued. it is seenthat each level of expansion will reduce the number of variables in theresidue function by k-l. Hence, if nl is divisible by k-l. then at thetth level of the modular realization, where t=(n l )/(kl the residuefunction is of the variable x, only and the expansion processterminates.

lfk-l does not divide n-l then some modification is necessary.

Let

Then f is expanded as follows:

connections for A (2'-' SrSfN-l) are don't-care. Each residue 55function in the above fomlula is a function of n-r variables, wheren-r-l is divisible by k-l. Thus, the previous procedure can be appliedto complete the modular realization of the ULC.

If more than one kind of Type I ULM is available, then the dont-careconnection can always be avoided. Suppose in addition to Type I ULM-ks,Type I ULMr is also available. Then, in the first expansion Type I ULM-ris used without don 't-care connection, and all the higher levelexpansion can use Type l ULM-ks. Or if Type I ULM-m is also available,65

where m=k+r, then the first and second level expansion mentioned beforecan be combined to one level by using a Type I ULM-m.

The modular realization of ULC using Type I ULC can readily be extendedto the use of Type II ULM by observing 70 the equation 2ll-I 1 I 0realization. the dont-care terminal connections can always be avoided.Furthermore, it is noted that the tree structure of the modularrealization ofa ULC ofn variables using ULM-ks always has 2" frontterminals in the last level for any k.

ULC WITH CONCURRENT ERROR-DETECTING PROPERTY A check bit can be appliedto a ULC to detect any single fault as shown in the circuit of FIG. 9.Each box B, is a ULC of nlt+l variables, 0$i 2"- 1 with thecorresponding outputs where i i ni is the binary representation of i.The methods for finding the appropriate values for terminals ls ..P "-twas described above in the portion identified ULC Modules of nVariables. The appropriate values over terminals Q ...,Q are found inthe same manner. A check bit b is applied to check every f,-(0 i$2""lHence we have b: 065 fi 6B f k-l whereGQdenotes the excl usive-ORoperation. Since each f,- is a function of n-k+l variables. x qc hx, bis also a function of 0 the same nll+l variables and can be produced bya ULC Bg of nk+l variables. The existence of a malfunctioning B 051's2"- 1 can be indicated by the output 2 of an exclusive-OR gate as shownin FIG. 9. Both the ULMk at the output of the circuit and theexclusive-OR gate have to be reliable and be built together in onehighly reliable package.

It is noted that this approach can be extended to concurrent errorcorrection for ULCs by using an error correcting code hereafter.

IMPROVING THE RELIABILITY OF THE MODULAR REALIZATION OF A ULC BY ANERROR-CORRECTING CODE The reliability of the modular realization of aULC can be improved by adding redundant ULMs using an error-correctingcode. In the present disclosure a single-error-correcting code is usedto increase the reliability of the modular realization of a ULC of nvariables, although the manner in which other codes can be used for alike purpose will be obvious therefrom. The circuit is shown in FIG. l0and the following notations are employed.

ffl-hrhvb-qh) fU r liv'n n) f,= 0, l,x ,...,x,,) f==( I, Is fs=( Lss-an.) The four blocks B B B and B are the modular realizations of theULCs of rr2 variables and have the outputs ji f f and f respectively.The single-error-correcting code with four information symbols is used,and its parity-check matrix H and generator matrix G are given by 0 0 0l l 1 1 H= O 1 1 0 0 1 l 1 0 1 O 1 0 1 (1) Pl P2 fl] P8 f1 f2 fa 1 1 l 00 0 0 G: 1 0 0 1 1 0 0 0 1 0 l 0 l 0 1 l 0 1 O 0 1 2) The fourinformation symbols to be encoded are f f f and f which are placed inthe 3rd, 5th, 6th and 7th positions of the 7-bit code word respectively,while the remaining three positions are theparity-check symbols p p 1 asshown in (2). It

follows from (I) and (2) that the parity check symbols p,,p and p, canbe expressed in terms Off f fg andf as follows:

weft/1t. MGM +1 try-1+ m r. Since fl,,f,,]'-, andf, are functions of then-2 variables .r,,,...,r,,, p,,p-, and p, are also functions of the samen-2 variables .r,.... r,.. Thus. each of p,.p- -.p can be realized byusing the modular realization of an ULC of n-2 variables. The three ULCsof n-Z variables for p,,p and 12 are represented by the blocks B,,B,,and 8,, shown in FIG. 10. The seven signalsfl f, fJ,,p,,p- ,p-, are thenfed to a decoder followed by a ULM-3 which produces the finaloutputflx,,...,r,,). The decoder and the ULM-3 connected to the outputterminal have to be of high reliability. lt is found that the decoderwill have seven exelusive-OR gates, three INVERTERS and four AND gates.The decoder can be implemented together with the ULM-3 in a singlereliable package. Let a block containing faulty ULM's be called a faultyblock. It is seen that such a ULC of n variables will give correctoutput for the case that there is more than one faulty block, providedthat only one erroneous block signal will show up at a time (under anyinput combination). if there exists a faulty block in the ULC, theeasiest way to detect this faulty block is to add three output terminalsto the decoder showing the syndrome of the code words. The faulty blockcan be located automatically by simply reading the syndrome when thefirst fault occurs during the use of the ULC, and no separate test isrequired. The increase of cost for implementing this scheme is that forany n 3, we have to add 75 percent redundant ULC's of n-2 variables andone highly reliable decoder-ULM-3 package. It is noted that the methodillustrated above can easily be extended to the use of Hamming code withmore than four information bits. Furthermore, the error-correcting codethat can be used for increasing the reliability of the ULC is notrestricted to the Hamming code, and the number of errors that can becorrected is not restricted to a single one.

CONCLUSION The foregoing disclosure sets forth universal logic circuitswhich are especially suitable to implementation by the use of integratedcircuit packages. Various effects, such as the number of pins, thenumber of logic gates and the number of logic levels in a package havebeen set forth. Furthermore, a method for improving the reliability ofaULC using error-correcting codes has been demonstrated.

lt is noted that an important practical advantage of using a ULC torealizing a given logic function is that there is no need to find theminimal sum or minimal product of the logic function, as has beenpreviously required in conventional realization methods. The onlysimplification process necessary to be applied to the logic function isto detect whether it can be written in a form which involves fewervariables. This result is used to determine a ULC of the smallest numberof variables for realizing the given logic function.

It should be pointed out that the ULCs disclosed herein are restrictedto realizing any single logic function. A natural extension of thisinvention is to use a multiple-output ULC for realizing any set of mlogic function. One way to obtain such a multiple-output ULC is toconnect the m ULC's, each of which realizes one of the m logicfunctions, in the form of sharing the common input-variable terminals.It is quite unlikely that a multiple-output ULC with fewer terminals canbe obtained, since in general there are no fixed relations among the mlogic functions to be realized.

We claim:

1. A universal logic circuit for providing the function for at leastthree variables .r,, x, and x compr ising input means including at leastone group of paths (2,, C, for providing x,, I, inputs, a second groupof paths C C, for providing x I, inputs, a third group of paths forproviding four separate inputs representing the residue functionsf(0,0,r)fl0, l g l/I l ,O c andfl l, l ,x ofa functionflx,, x x,,) of threevariables 1,, x and x expanded as functions of x, only; at least fourlogic gates comprising one gate connected to the paths for the I I, andf(0,0,x;,) inputs, a second gate connected to the paths for the Y x,,f(0,l ,.Xg) inputs, a third gate connected to the paths for the x,, 17,11 l,0,x,,) inputs, and a fourth gate connected to the paths for thex,, x fl l, l ,.x,,) inputs, and output means connected to combine theoutputs of said four gates.

2. A universal logic circuit as set forth in claim 1 in which said inputmeans includes six input terminals for said logic circuit, comprising afirst input terminal for input x,, a second input terminal for x,, andfour separate terminals for said four residue functions, and invertermeans connected to said C C, input terminals to provide said Z, I,signals for said 6,, C paths.

3. A universal logic circuit as set forth in claim 1 in which each ofsaid logic gates includes a diode for each input thereto, and saidoutput means including a plurality of semiconductor devices, each devicerespectively connected to the output of the diodes in an associatedgate.

4. A universal logic circuit as set forth in claim 1 in which the numberof variables is n=3, and the number of input pins p is 2"- +1=6.

5. A universal logic circuit for providing the function for at leastfour variables x,, x x and x, comprising input means including at leastone group of input paths C,, C for providing x,, 2?, inputs, a secondgroup of input paths C,, Q, for providing x,, X, inputs, a third groupof input paths C C;, for providing it If, inputs, and a fourth group ofpaths for each of the residue functions of ft x, x, x, x,) expanded asfunctions of at, only, at least eight logic gates comprising one gateconnected to input paths for I 3 E and fl0,O,0,x a second gate connectedto the input paths for I 2 x and fl0,0,l,x a third gate connected to theinput paths for 35,, x I, and f(0,l ,0,x,), a fourth gate connected tothe input paths for 17,, x x and f(0, 1,1, a fifth gate connected to theinput paths for x,, an. I, and fl l,0,0,x,), a sixth gate connected tothe input paths for x,, L, x, andfl 1,0, l ,x a seventh gate connectedto the input paths for .r,, x I, andfl l, l ,O an eighth gate connectedto the input paths for x,, x x andfl l ,l,l,r,), and output means forcombining the function outputs provided by said eight gates.

6. A universal logic circuit as set forth in claim 5 in which each ofsaid eight gates is connected to only the paths for providing said x.,t;,,f ,ir' inputs and the indicated residue functions, and whichincludes a first additional gate means con nected to the outputs of afirst plurality of said eight gates and said 1:, input, and a secondadditional gate means connected to the outputs of the remaining one ofsaid eight gates and said x, input, and in which the output of saidfirst and second additional gate means is connected to said outputmeans.

7. A universal logic circuit for providing the function for a pluralityof n variables x,, x ,...,x,, comp ising input means including at leastone group of paths C C, for providing an, 3:, inputs, a second group ofpaths C C for providing 1: It, inputs, a third group of paths forproviding at least four separate inputs representing the residuefunctionsfl0,0,...,x,,),fl0,l x,,),f( l,0,...,x,,), andfl l,l,...,x,,)ofa functionf(.r,,.r,,...,x,,) of n variables x,, x,,...,x,, expanded asa function of x, only; at least four logic gates comprising one gateconnected at least to the paths for the 3,, I and j(0,0,...,r,,) inputs,a second gate connected at least to the paths for the I,,x ,j(0, l,...,x,,) inputs a third gate connected to at least the paths for the1,, 5, f( l,0,...,x,,) inputs, and a fourth gate connected to at leastthe paths for the x,, x ,f(l,l ,...,x,,) inputs, and a fourth gateconnected to at least the paths for the x,, 1,, x,,x,,f( 1,1 ,...,x,,)inputs, and output means connected to combine the outputs of said gates.

8. A Universal logic circuit as set forth in claim 7 in which the numberof variables is n and the number of input pins p is 2""+nl.

9. In a circuit as set forth in claim 7 in which the number of inputs toeach oflevels l is gate is limited to four and in which the number whenn is Odtl -1 when n is even forth in claim 7 in which the number oflimited to four. and which has q gates ll. A universal logic circuit forvariables comprising input ofinput terminals Ct, Ca... 0,, c,, a secondgroup A,,.... A connected to providing the function for n meansincluding at least one group Cu for providing input variables ofseparate input terminals A". provide different input variables ri i.ri ua plurality of logic gates responsive to the inputs on said input tetmiconnected to provide a function d at an output terminal F, in

12. In a circuit as set =q in whichj=l.2....nl.

forth in claim ll in which the total number of input terminals ,9 isp=2" '+nal.

B. A universal logic ci said logic gates are ar combinations of saidrcuit as set forth in claim 11 in which ranged in modules, and whichincludes input terminals C,, CH4 and said plurality ofA terminals.

14. A universal logic circuit as set forth in claim I I in which saidlogic gates are means connecting said arranged in modules, and whichincludes modules in a series of successive levels.

and means connecting the input to the modules in the last level to saidinput terminals A ,A.

two of said input termi ,Az' k, and to at least 15. A universal logiccircuit as set forth in claim 14 in which least one module having inputsconnected in different combinations to the outputs ofa module in apreceding terminals.

16. A system as set level of said modules p level, and to at least twoofsaid C input forth in claim [4 in which the second roduce a pluralityof residue functions f,

of nk+l variables as inputs to said first level in which It is thenumber of eludes means for functions L, and

provi variables in the first level module, and which inding a check bitb to check each of said detector means responsive to said check bit andsaid function f, to detect a fault prior to said first level.

17. A system as set forth in claim 16 which includes means for providinga plurality the residue function f,- means responsive to s of check bitSP), the check bits with providing a parity check code, decoder aidparity check bits and said residue functions to correct each function/1.and means connecting the output of said decoder means to said firstlevel module 18. A universal logic circuit for provtdmg the function forn variables comprising input means including at least one 2 of inputterminals (RF-1.. (1H for providing input variables m.

q.....c,,..,,. a second group of separate input terminals A...

A A connected to provide different input variables llujltllg t aplurality of logic gates connected to heresponsive to the inputs on sa ii np u t terminals C (":....C

and AttAt. A! to provide a function 0,, at :in output terminals F. inwhich 1 P E f tg 3:

where the superscripts not. form the binary representution off. andc,-"=c',. 0 in whichj== .11....u-l.

[9. In a universal logic circuit. a first input path. a second inputpath. a third input path. and a fourth input path. a plurality of atleast four separate additional input circuits providing four differentinput functions, a first logic gate having at least three inputsincluding means for connecting one of its inputs to said second inputpath. a second one of its inputs to said fourth input path and a thirdone of its inputs to one of said four separate input circuits; a secondlogic gate having three inputs including means for connecting one of itsinputs to said second input path. a second one of its inputs to saidthird input path and a third one of its inputs to a second one of saidfour separate input circuits; a third logic gate having at least threeinputs including means for connecting one of its inputs to said firstinput path, a second one of its inputs to said fourth input path and athird one of its inputs to a third one of said four separate inputcircuits; and a fourth gate having at least three inputs including meansfor connecting a first one of its inputs to said first input path, asecond one of its inputs to said third input path, and a third one ofits inputs to the fourth one of said four separate input circuits.

20. A circuit as set forth in claim 19 in which said first, second.third and fourth paths are connected to provide x,, L, x,. f, variablesignals to the circuit, and said input circuits are connected to providefour different residue functions.

21. In a universal logic circuit for providing the function for nvariables comprising a first input path for providing one vari able in,a second necting a first one of its inputs to said I, input path, asecond one of its inputs to said x input path and its third input to asecond one of said four separate input circuits, a third logic gatehaving at least three inputs including means for connecting a first oneof its inputs to said it. input path. a second one x. input path, asecond one of its inputs to said 1 input path, and its third input tothe remaining one of said four separate input circuits.

1. A universal logic circuit for providing the function for at leastthree variables x1, x2 and x3 comprising input means including at leastone group of paths C1, C1 for providing x1, x1 inputs, a second group ofpaths C2, C2 for providing x2, x2 inputs, a third group of paths forproviding four separate inputs representing the residue functionsf(0,0,x3) f(0,1,x3) f(1,0,x3) and f(1,1,x3) of a function f(x1, x2, x3)of three variables x1, x2, and x3 expanded as functions of x3 only; atleast four logic gates comprising one gate connected to the paths forthe x1, x2 and f(0,0,x3) inputs, a second gate connected to the pathsfor the x1, x2, f(0,1,x3) inputs, a third gate connected to the pathsfor the x1, x2, f(1,0,x3) inputs, and a fourth gate connected to thepaths for the x1, x2, f(1,1,x3) inputs, and output means connected tocombine the outputs of said four gates.
 2. A universal logic circuit asset forth in claim 1 in which said input means includes six inputterminals for said logic circuit, comprising a first input terminal forinput x1, a second input terminal for x2, and four separate terminalsfor said four residue functions, and inverter means connected to saidC1, C2 input terminals to provide said x1, x2 signals for said C1, C2paths.
 3. A universal logic circuit as set forth in claim 1 in whicheach of said logic gates includes a diode for each input thereto, andsaid output means including a plurality of semiconductor devices, eachdevice respectively connected to the output of the diodes in anassociated gate.
 4. A universal logic circuit as set forth in claim 1 inwhich the number of variables is n 3, and the number of input pins p is2n 1+n-1
 6. 5. A universal logic circuit for providing the function forat least four variables x1, x2, x3 and x4 comprising input meansincluding at least one group of input paths C1, C1 for providing x1, x1inputs, a second group of input paths C2, C2 for providing x2, x2inputs, a third group of input paths C3, C3 for providing x3, x3 inputs,and a fourth group oF paths for each of the residue functions of f(x1 x2x3 x4) expanded as functions of x4 only, at least eight logic gatescomprising one gate connected to input paths for x1, x2, x3 andf(0,0,0,x4), a second gate connected to the input paths for x1, x2, x3and f(0,0,1,x4), a third gate connected to the input paths for x1, x2,x3 and f(0,1, 0,x4), a fourth gate connected to the input paths for x1,x2, x3 and f(0,1,1,x4), a fifth gate connected to the input paths forx1, x2, x3 and f(1,0,0,x4), a sixth gate connected to the input pathsfor x1, x2, x3 and f(1,0,1,x4), a seventh gate connected to the inputpaths for x1, x2, x3 and f(1,1,0,x4), an eighth gate connected to theinput paths for x1, x2, x3 and f(1,1,1,x4), and output means forcombining the function outputs provided by said eight gates.
 6. Auniversal logic circuit as set forth in claim 5 in which each of saideight gates is connected to only the paths for providing saidx2,x3,x2,x3 inputs and the indicated residue functions, and whichincludes a first additional gate means connected to the outputs of afirst plurality of said eight gates and said x1 input, and a secondadditional gate means connected to the outputs of the remaining one ofsaid eight gates and said x1 input, and in which the output of saidfirst and second additional gate means is connected to said outputmeans.
 7. A universal logic circuit for providing the function for aplurality of n variables x1, x2,...,xn comprising input means includingat least one group of paths C1, C1 for providing x1, x1 inputs, a secondgroup of paths C2, C2 for providing x2, x2 inputs, a third group ofpaths for providing at least four separate inputs representing theresidue functions f(0,0,...,xn), f(0,1,...,xn), f(1,0,...,xn), andf(1,1,...,xn) of a function f(x1,x2,...,xn) of n variables x1, x2,...,xnexpanded as a function of xn only; at least four logic gates comprisingone gate connected at least to the paths for the x1, x2 and f(0,0,...,xn) inputs, a second gate connected at least to the paths for thex1,x2, f(0,1,...,xn) inputs a third gate connected to at least the pathsfor the x1, x2, f(1,0,...,xn) inputs, and a fourth gate connected to atleast the paths for the x1, x2, f(1, 1,...,xn) inputs, and a fourth gateconnected to at least the paths for the x1, x2, x1,x2, f(1,1,...,xn)inputs, and output means connected to combine the outputs of said gates.8. A Universal logic circuit as set forth in claim 7 in which the numberof variables is n and the number of input pins p is 2n 1+n-1.
 9. In acircuit as set forth in claim 7 in which the number of inputs to eachgate is limited to four and in which the number of levels l is
 10. In acircuit as set forth in claim 7 in which the number of inputs to eachgate is limited to four, and which has q gates when